1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and, more particularly, to a method of fabricating a fast bipolar transistor whose base layer is epitaxially grown.
2. Description of the Related Art
In methods of forming the bases of transistors by epitaxial growth, an SEEW (Selective Epitaxy Emitter Window) technique is known as a method of forming the bases and emitters using a selfalign technique. FIG. 13 presents a cross-sectional view for explaining a conventional method of fabricating a semiconductor device, which employs this SEEW technique. The method is disclosed in U.S. application Ser. No. 219,020, filed Jul. 14, 1988.
First, buried oxide films 2 are provide on an N.sup.- type silicon substrate (collector region) 1o Next, an epitaxial layer (P.sup.++ type base region) 3 is grown on the surface of this N.sup.- type silicon substrate 1, with a first polysilicon layers (P.sup.++ type base region) 4 grown on the buried oxide films 2. After this step, a silicon oxide film 5 is provided on the epitaxial layer 3 and the first polysilicon layers 4, and a silicon nitride film 6 is formed on this silicon oxide film 5. Then, the silicon nitride film 6 and the silicon oxide film 5 are so etched as to remain only on the epitaxial layer that lies the area between the buried oxide films 2.
After this etching, a second polysilicon layer 7 is deposited on this silicon nitride film 6, epitaxial layer 3 and first polysilicon layers 4. Next, a first opening 7a is formed in the second polysilicon layer 7 above the silicon nitride film 6. Then, a thermal oxide film 10 is formed on the surface of the polysilicon layer 7. A second opening 6a is bored in the silicon nitride film 6 and silicon oxide film 5 under the first opening 7a, thereby exposing a part of the epitaxial layer 3.
A P.sup.+ type substantial base region 8 is formed in the epitaxial layer 3 below the second opening 6a. After this step, with the polysilicon layer 7 as a mask, impurity ions are injected in the substantial base region 8 of the epitaxial layer 3 to form an N.sup.+ type emitter region 9 below the second opening 6a. A conductive third polysilicon layer 11 is then formed on this emitter region 9 and the thermal oxide film 10.
According to this first conventional method of fabricating a semiconductor device, while the substantial base region 8 and emitter region 9 are formed by the selfaligned technique, the base region 3 is not selfaligned to the buried oxide film 2 which defines the base region 3. Accordingly, the base-collector capacitance increases. Although the emitter width is controlled by using the horizontal selective growth, the reproducibility of the process at this time is generally poor.
FIG. 14 is a cross-sectional view for explaining a second conventional method of fabricating a semi-conductor device. The method is disclosed in U.S. Pat. No. 4,592,933. First, an N.sup.- type diffusion layer 15 for the collector is formed on an N.sup.+ type region 14 on a silicon substrate 13. Next, an N type region 16 is formed on the surface of this N.sup.- type diffusion layer 15. Then, a silicon oxide film 17 is deposited on the surface of the silicon substrate 13, and a silicon nitride film 18 is deposited on this silicon oxide film 17. Next, a first polysilicon film 19 for leading out the base is deposited on this silicon nitride film 18, with a first oxide film 20 formed on the first polysilicon film 19. After this step, a first nitride film 21 is formed on this first oxide film 20. Then, an opening 21a is bored in the first nitride film 21, first oxide film 20, first polysilicon film 19, silicon nitride film 18 and silicon oxide film 17 above the N type region 16.
Then, a P type polycrystalline silicon layer 22 is formed on the side wall of this opening 21a where the first polysilicon film 19, silicon nitride film 18 and silicon oxide film 17 are exposed, and a P type epitaxial layer 23 for the base is formed by epitaxial growth on the surface of the N type region 16 which is exposed to the bottom of the opening 21a. Next, a second oxide film 20a is formed on this P type epitaxial layer 23 and the P type silicon layer 22, with a second nitride film 21b formed on this second oxide film 20a. After this step, a second polysilicon film 24 is formed on that portion of the second nitride film 21b which corresponds to the side wall of the opening 21a. With this second polysilicon film 24 used as a mask, the second nitride film 21b and second oxide film 20a are etched to expose a part of the P type epitaxial layer 23. Then, an N.sup.+ type polysilicon film 25 for the emitter is formed on this exposed P type epitaxial layer 12, the second polysilicon film 24 and the first nitride film 21.
According to this second conventional semiconductor device fabrication method, the opening 21a is formed in the first nitride film 21, the first oxide film 20, the first polysilicon film 19, the silicon nitride film 18 and the silicon oxide film 17, and the base region 23 and emitter region 25 are formed in a selfaligned manner to the opening 21a. Therefore, the base-emitter capacitance can be made idealistically very small. Because this fabrication method is considerably complicated as is apparent from the above, the control of the manufacturing process is difficult and the manufacturing cost increases.
The semiconductor device fabricated by this method however requires that the base layer should be made thin in order to improve the performance of transistors. In this case, as the base region 23 is made thinner, the P type silicon layer 22 on the side wall of the opening 21a becomes thinner. This increases the resistance of the P type silicon layer 22, thus making it very difficult to stabilize the contact between the base region 23 and the polysilicon film 19 for leading out the base.